Seil

PCB - Multi-Layer

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Seil
[Korea]

Address
9, Yeonmujang 13-gil, Seongdong-gu, Seoul
Phone
82-10-42373958
Contact name
SONG CHANG KEUN

Quick Information

  • Place of Origin: Korea
  • :

Description

PCB - Multi-Layer
Description
A multilayer printed circuit board (PCB) is a PCB made by laminating three or more layers (typically four, six, or eight or more) of copper foil with an insulating layer (prepreg). The inner and outer layers (top and bottom) are connected with vias to create high-density, high-performance circuits. A multilayer PCB is a printed circuit board structure optimized for products requiring high-density, high-performance, and low-noise.
Specifications
Layer Count
• Typical Range: 4, 6, 8, 10, 12+ Layers
• Meaning: More layers mean better circuit density, power/ground separation, and EMI performance.

Selection Guide
• 4 Layers: General control/medium-speed signals
• 6-8 Layers: High-speed digital, communications
• 10+ Layers: High-performance computing/servers/automotive electronics

Base Material
• FR-4 (Standard/High Tg): General Purpose, Excellent Cost-Performance
• High-Tg FR-4: Enhanced Thermal and Reliability
• Low Dk/Low Df Material: For High-Speed/High-Frequency Signals

Selection Guide
• High-Speed/High-Frequency → Low Dk/Df
• High-Temperature Environments → High-Tg

Board Thickness
• Typical range: 0.8–3.2 mm
• Standard: 1.6 mm (varies depending on number of layers and application)

Influencing factors
Mechanical stiffness, impedance control, heat generation

Copper Weight
• Outer Layer: 0.5 to 1 oz (typical), up to 2 oz
• Inner Layer: 0.5 to 1 oz

Selection criteria
• Signal Layer: Thin (impedance-precise)
• Power Layer: Thick (current- and heat-resistant)

Lines & Spaces
• Standard: 100–150 μm
• Minimum: 75 μm or less (HDI process)

Influencing factors
Manufacturing difficulty, cost, and yield

Via Specifications

• Through Via (PTH): General Purpose
• Blind/Buried Via: High-Density Design
• Micro Via (HDI): Ultra-High-Density Design

Selection Guide
Micro/Blind Via Utilization for Area-Saving and High-Speed Designs

Stack-up desgin
• Separate signal, power, and ground layers
• Symmetrical structure minimizes warping
• Impedance control (differential and single)

Benefits
Improved signal integrity/precision, reduced EMI

Surface Finish
• ENIG: Excellent flatness and reliability (recommended)
• OSP: Low cost and short-term use
• Im Silver / Im Tin: Focus on flatness

Solder Mask

• Colors: Green, Black, White, etc.
• Green: Highest stability and cost-effectiveness

Electrical Test

• 100% BBT: Open/Short Inspection
• Full inspection is required for higher floors.

Technical Data
Item General Specifications
Layer 4~12+
Material FR-4 / High-Tg / Low Dk·Df
Thickness 0.8~3.2mm
Copper Foil 0.5~2 oz
Line WIdth/Pitch 150~200 μm (Minimum 100 μm)
Via PTH / Blind / Buried / Micro
Solder Mask ENIG recommended
Test BBT transfer


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